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Ordering number : EN5915A
CMOS IC
LC75811E, 75811W
1/8 to 1/10 Duty Dot Matrix LCD Display Controller/Driver
Overview
The LC75811E and LC75811W are 1/8 to 1/10 duty dot matrix LCD display controller/drivers that supports the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC75811E and LC75811W also provide on-chip character display ROM and RAM to allow display systems to be implemented easily.
Package Dimensions
unit: mm 3174-QFP80E
[LC75811E]
Features
* Controls and drives a 5 x 7, 5 x 8, or 5 x 9 dot matrix LCD. * Supports accessory display segment drive (up to 60 segments) * Display technique: 1/8 duty 1/4 bias drive (5 x 7 dots) 1/9 duty 1/4 bias drive (5 x 8 dots) 1/10 duty 1/4 bias drive (5 x 9 dots) * Display digits: 12 digits x 1 line (5 x 7 dots), 11 digits x 1 line (5 x 8 or 5 x 9 dots) * Display control memory CGROM: 240 characters (5 x 7, 5 x 8, or 5 x 9 dots) CGRAM: 16 characters (5 x 7, 5 x 8, or 5 x 9 dots) ADRAM: 12 x 5 bits DCRAM: 48 x 8 bits * Instruction function Display on/off control Display shift function * Provides a backup function based on low power modes. * Serial data input supports CCB format communication with the system controller. * Independent LCD drive block power supply VLCD * Provides a RES pin for LSI internal initialization * RC oscillator circuit
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO: QFP80E
unit: mm 3220-SQFP80
[LC75811W]
SANYO: SQFP80
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1098RM (OT) No. 5915-1/27
LC75811E, 75811W Pin Assignments (Top View)
LC75811E
LC75811W
No. 5915-2/27
LC75811E, 75811W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VLCD max VIN1 Input voltage VIN2 VIN3 Output voltage VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg VDD VLCD CE, CL, DI, RES OSCI VLCD1, VLCD2, VLCD3 OSCO S1 to S60, COM1 to COM10 S1 to S60 COM1 to COM10 Ta = 85C Conditions Ratings -0.3 to +7.0 -0.3 to +11.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VLCD + 0.3 -0.3 to VDD + 0.3 -0.3 to VLCD + 0.3 300 3 200 -40 to +85 -55 to +125 Unit V V V V V V V A mA mW C C
Output current Allowable power dissipation Operating temperature Storage temperature
Allowable Operating Ranges at Ta = -40 to 85C, VSS = 0 V
Parameter Symbol VDD VLCD VLCD1 Input voltage VLCD2 VLCD3 Input high level voltage VIH1 VIH2 VIL1 VIL2 ROSC COSC fOSC tds tdh tcp tcs tch toH toL tWRES VDD VLCD VLCD1 VLCD2 VLCD3 CE, CL, DI, RES OSCI CE, CL, DI, RES OSCI OSCI, OSCO OSCI, OSCO OSC CL, DI: Figure 2 CL, DI: Figure 2 CE, CL: Figure 2 CE, CL: Figure 2 CE, CL: Figure 2 CL: Figure 2 CL: Figure 2 RES: Figure 3 150 160 160 160 160 160 160 160 1 0.8 VDD 0.7 VDD 0 0 33 220 300 600 Conditions Ratings min 2.7 4.5 3/4 VLCD 2/4 VLCD 1/4 VLCD typ max 6.0 10.0 VLCD VLCD VLCD 6.0 VDD 0.2 VDD 0.3 VDD Unit V V V V V V V V V k pF kHz ns ns ns ns ns ns ns s
Supply voltage
Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Minimum reset pulse width
No. 5915-3/27
LC75811E, 75811W Electrical Characteristics in the Allowable Operating Ranges
Parameter Hysteresis Input high level current Input low level current Symbol VH IIH IIL VOH1 Output high level voltage VOH2 VOH3 VOL1 Output low level voltage VOL2 VOL3 VMID1 Output middle level voltage*1 VMID2 VMID3 Oscillator frequency fOSC IDD1 Current drain IDD2 ILCD1 ILCD2 CE, CL, DI, RES CE, CL, DI, RES, OSCI: VI = 6.0 V CE, CL, DI, RES, OSCI: VI = 0 V S1 to S60: IO = -20 A COM1 to COM10: IO = -100 A OSCO: IO = -500 A S1 to S60: IO = 20 A COM1 to COM10: IO = 100 A OSCO: IO = 500 A S1 to S60: IO 20 A COM1 to COM10: IO = 100 A COM1 to COM10: IO = 100 A OSCI, OSCO: ROSC = 33 k, COSC = 220 pF VDD: power saving mode VDD: VDD = 6.0 V, output open, fOSC = 300 kHz VLCD: power saving mode VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz 200 450 2/4 VLCD - 0.6 3/4 VLCD - 0.6 1/4 VLCD - 0.6 210 300 -5.0 VLCD - 0.6 VLCD - 0.6 VDD - 1.0 0.6 0.6 1.0 2/4 VLCD + 0.6 3/4 VLCD + 0.6 1/4 VLCD + 0.6 390 5 900 5 400 Conditions Ratings min typ 0.1 VDD 5.0 max Unit V A A V V V V V V V V V kHz A A A A
Note *1: Excluding the bias voltage generation divider resistor built into the VLCD1, VLCD2, and VLCD3. (See figure 1.)
To the common and segment drivers
Excluding these resistors
Figure 1
No. 5915-4/27
LC75811E, 75811W * When CL is stopped at the low level
* When CL is stopped at the high level
Figure 2 Block Diagram
No. 5915-5/27
LC75811E, 75811W Pin Functions
Pin No. Pin S1 to S58 LC75811E 1 to 58 LC75811W 79, 80 1 to 56 S59/COM10 S60/COM9 COM1 to COM8 OSCI OSCO CE CL DI 59 60 68 to 61 76 75 78 79 80 57 58 66 to 59 74 73 76 77 78 Common driver outputs. Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor at these pins. Serial data transfer inputs. These pins are connected to the microcontroller. CE: Chip enable CL: Synchronization clock DI: Transfer data Reset signal input. * When RES is low (VSS): * Display off S1 to S58 = "L" (VSS). S59/COM10 and S60/COM9 = "L" (VSS). COM1 to COM8 = "L" (VSS). * Serial data transfer is disabled. * The OSCI/OSCO pin oscillator is stopped. * When RES is high (VDD): * Display on after a "display on/off control" (display on state setting) instruction is executed. * Serial data transfers are enabled. * The OSCI/OSCO pin oscillator operates. Used for applying the LCD drive 3/4 bias voltage externally. Used for applying the LCD drive 2/4 bias voltage externally. Used for applying the LCD drive 1/4 bias voltage externally. Logic block power supply connection. Provide a voltage of between 2.7 and 6.0 V. LCD driver block power supply connection. Provide a voltage of between 4.5 and 10.0 V. Power supply connection. Connect to ground. -- -- -- H O I O I I -- I GND OPEN GND OPEN Segment driver outputs. The S59/COM10 and S60/COM9 pins can be used as common driver outputs under the "set display technique" instruction. -- O OPEN Function Active I/O Handling when unused
RES
77
75
L
I
GND
VLCD1 VLCD2 VLCD3 VDD VLCD VSS
71 72 73 69 70 74
69 70 71 67 68 72
-- -- -- -- -- --
I I I -- -- --
OPEN OPEN OPEN -- -- --
No. 5915-6/27
LC75811E, 75811W Block Functions * AC (address counter) AC is a counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained. * DCRAM (data control RAM) DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 48 x 8 bits, and can hold 48 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel. * When the DCRAM address loaded into AC is 00H.
Display digit DCRAM address (hexadecimal) 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B
However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below.
Display digit DCRAM address (hexadecimal) Display digit DCRAM address (hexadecimal) 1 01 1 2F 2 02 2 00 3 03 3 01 4 04 4 02 5 05 5 03 6 06 6 04 7 07 7 05 8 08 8 06 9 09 9 07 10 0A 10 08 11 0B 11 09 12 0C 12 0A (Right shift) (Left shift)
Note:*2. The DCRAM addresses are expressed in hexadecimal.
Least significant bit LSB DCRAM address DA0 DA1 DA2 DA3 DA4 Most significant bit MSB DA5
Hexadecimal
Hexadecimal
Example: When the DCRAM address is 2EH.
DA0 0 DA1 1 DA2 1 DA3 1 DA4 0 DA5 1
Note:*3. 5 x 7 dots ... 12-digit display 5 x 8 dots ... 12-digit display 5 x 9 dots ... 12-digit display
5 x 7 dots 4 x 8 dots 3 x 9 dots
No. 5915-7/27
LC75811E, 75811W * ADRAM (Additional data RAM) ADRAM is RAM used to store the ADATA display data. ADRAM has a capacity of 12 x 5 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel. * When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 12)
Display digit ADRAM address (hexadecimal) 1 0 2 1 3 2 4 3 5 4 6 5 7 6 8 7 9 8 10 9 11 A 12 B
However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below.
Display digit ADRAM address (hexadecimal) Display digit ADRAM address (hexadecimal) 1 1 1 B 2 2 2 0 3 3 3 1 4 4 4 2 5 5 5 3 6 6 6 4 7 7 7 5 8 8 8 6 9 9 9 7 10 A 10 8 11 B 11 9 12 0 12 A (Right shift) (Left shift)
Note: *4. The ADRAM addresses are expressed in hexadecimal.
Least significant bit LSB ADRAM address RA0 RA1 RA2 Most significant bit MSB RA3
Hexadecimal
Example: When the ADRAM address is AH
RA0 0 RA1 1 RA2 0 RA3 1
Note: *5. 5 x 7 dots ... 12-digit display 5 x 8 dots ... 12-digit display 5 x 9 dots ... 12-digit display
5 dots 4 dots 3 dots
* CGROM (Character generator ROM) CGROM is ROM used to generate the 240 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 240 x 45 bits. When a character code is written to DCRAM, the character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC. * CGRAM (Character generator RAM) CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 x 7, 5 x 8, or 5 x 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 x 45 bits.
No. 5915-8/27
LC75811E, 75811W Reset Function The LC75811E and LC75811W are reset when a low level is applied to the RES pin at power on and, in normal mode. On a reset the LC75811E and LC75811W create a display with all LCD panels turned off. However, after a reset applications must set the contents of DCRAM, ADRAM, and CGRAM before turning on display with a "display on/off control" instruction since the contents of these memories are undefined. That is, applications must execute the following instructions. * * * * * Set display technique DCRAM data write ADRAM data write (If ADRAM is used.) CGRAM data write (If CGRAM is used.) Set AC address
After executing the above instructions, applications must turn on the display with a "display on/off control" instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a "display on/off control" instruction. (See the detailed instruction descriptions.) Serial Data Transfer Format * When CL is stopped at the low level
CCB address 8 bits
Instruction data Up to 64 bits
* When CL is stopped at the high level
CCB address 8 bits
Instruction data Up to 64 bits
* CCB address: 47H * D0 to D63: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.
No. 5915-9/27
Instruction Table
D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 Execution time *8 D58 D59 D60 D61 D62 D63
Instruction
D0 D1...D39
D40
D41
Set display technique
DT1 DT2
X
X
0
0
0
1
0 s
Display on/off control
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12
X
X
X
X
M
A
SC
BU
0
0
1
0
0 s/27 s *9
Display shift
M
A
R/L
X
0
0
1
1
27 s
Set AC address
DA0 DA1 DA2 DA3 DA4 DA5
X
X
RA0 RA1 RA2 RA3
0
1
0
0
27 s
DCRAM data write *6 X X
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
IM
X
X
X
0
1
0
1
27 s
ADRAM data write *7 X X X RA0 RA1 RA2 RA3 X X X X
AD1 AD2 AD3 AD4 AD5
IM
X
X
X
0
1
1
0
27 s
CGRAM data write
CD1 CD2...CD40
CD41 CD42 CD43 CD44 CD45
X
X
X
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
X
X
X
X
0
1
1
1
27 s X: don't care
LC75811E, 75811W
Notes:*6.The data format differs when the "DCRAM data write" instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions .) *7.The data format differs when the "ADRAM data write" instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions.) *8.The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs. Example: When fosc = 210 kHz 300 27 s x ---- = 39 s 210 *9.When the power saving mode (BU = 1) is set, the execution time is 27 s (when fosc = 300 kHz).
No. 5915-10/27
LC75811E, 75811W Detailed Instruction Descriptions * Set display technique ...
Code D56 D57 D58 X D59 X D60 0 D61 0 D62 D63 0 1
DT1 DT2
X: don't care
DT1, DT2: Setting the display technique
DT1 0 1 0 DT2 0 0 1 Display technique 1/8 duty, 1/4 bias drive 1/9 duty, 1/4 bias drive 1/10 duty, 1/4 bias drive Output pins S60/COM9 S60 COM9 COM9 S59/COM10 S59 S59 COM10 Note: *10. Sn (n = 59, 60): Segment outputs COMn (n = 9, 10): Common outputs
* Display on/off control ...
Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 X D53 X D54 X D55 X D56 M D57 A D58 SC D59 D60 BU 0 D61 0 D62 1 D63 0
DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12
X: don't care
M, A: Specifies the data to be turned on or off.
M 0 0 1 1 A 0 1 0 1 Display operating state Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG12 data.) Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG12 data are turned on.) Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG12 data are turned on.) Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG12 data are turned on.)
Note: *11. MDATA, ADATA 5 x 7 dot matrix display 5 x 8 dot matrix display 5 x 9 dot matrix display
DG1 to DG12: Specifies the display digit
Display digit Display digit data 1 DG1 2 DG2 3 DG3 4 DG4 5 DG5 6 DG6 7 DG7 8 DG8 9 10 11 12 DG9 DG10 DG11 DG12
For example, if DG1 to DG6 are 1, and DG7 to DG12 are 0, then display digits 1 to 6 will be turned on, and display digits 7 to 12 will be turned off (blanked).
No. 5915-11/27
LC75811E, 75811W SC: Controls the common and segment output pins.
SC 0 1 Common and segment output pin states Output of LCD drive waveforms Fixed at the VSS level (all segments off)
Note: *12. When SC is 1, the S1 to S60 and COM1 to COM10 output pins are set to the VSS level, regardless of the M, A, and DG1 to DG12 data.
BU: Controls the normal mode and power saving mode.
BU 0 Normal mode Power saving mode (In this mode, the OSCI and OSCO pins oscillator is stopped, and the common and segment pins are set to the VSS level. In this mode, instructions other than the "display on/off control" instruction cannot be executed. Thus applications must set the LSI to normal mode before executing any of the other instructions.) Mode
1
* Display shift ...
Code D56 M D57 A D58 R/L D59 X D60 0 D61 0 D62 D63 1 1 X: don't care
M, A: Specifies the data to be shifted
M 0 0 1 1 A 0 1 0 1 Shift operating state Neither MDATA nor ADATA is shifted Only ADATA is shifted Only MDATA is shifted Both MDATA and ADATA are shifted
R/L: Shift direction specification
R/L 0 1 Shift direction Left shift Right shift
* Set AC address...
Code D48 D49 D50 D51 D52 D53 D54 X D55 X D56 D57 D58 D59 D60 0 D61 1 D62 0 D63 0
DA0 DA1 DA2 DA3 DA4 DA5
RA0 RA1 RA2 RA3
X: don't care
DA0 to DA5: DCRAM address
DA0 DA1 DA2 DA3 DA4 DA5 LSB Least significant bit MSB Most significant bit
RA0 to RA3: ADRAM address
RA0 RA1 RA2 RA3 LSB Least significant bit MSB Most significant bit
This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC.
No. 5915-12/27
LC75811E, 75811W * DCRAM data write ...
Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 X D55 X D56 IM D57 X D58 X D59 D60 X 0 D61 1 D62 0 D63 1
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
X: don't care
DA0 to DA5: DCRAM address
DA0 DA1 DA2 DA3 DA4 DA5 LSB Least significant bit MSB Most significant bit
AC0 to AC7: DCRAM data (character code)
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 MSB Most significant bit LSB Least significant bit
This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 5 x 7, 5 x 8, or 5 x 9 dot matrix display data using CGROM or CGRAM. IM: Setting the method of writing data to DCRAM
IM 0 1 DCRAM data write method Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) Increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.)
Notes: *13. * DCRAM data write method when IM = 0
CCB address (1) 24 bits Instruction execution time
CCB address (1) 24 bits Instruction execution time
CCB address (1) 24 bits Instruction execution time DCRAM data write finishes
CCB address (1) 24 bits Instruction execution time DCRAM data write finishes
DCRAM data write finishes
DCRAM data write finishes
* DCRAM data write method when IM = 1 (Instructions other than the "DCRAM data write" instruction cannot be executed.)
CCB address (1) 24 bits
CCB address (2) 8 bits
CCB address (2) 8 bits
CCB address (2) 8 bits
CCB address (2) 8 bits
CCB address (3) 16 bits
Instruction execution time DCRAM data write finishes
Instruction execution time
Instruction execution time
Instruction execution time
Instruction execution time
Instruction execution time DCRAM dat write finishes
DCRAM data write finishes
DCRAM data write finishes
DCRAM data write finishes
DCRAM data write finishes
Instructions other than the "DCRAM data write" instruction cannot be executed.
A10721
No. 5915-13/27
LC75811E, 75811W Data format at (1) (24 bits)
Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 X D55 X D56 IM D57 X D58 X D59 D60 X 0 D61 1 D62 0 D63 1
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5
X: don't care
Data format at (2) (8 bits)
Code D56 D57 D58 D59 D60 D61 D62 D63
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
Data format at (3) (16 bits)
Code D48 D49 D50 D51 D52 D53 D54 D55 D56 0 D57 X D58 X D59 X D60 0 D61 1 D62 0 D63 1
AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7
X: don't care
* ADRAM data write ...
Code D40 D41 D42 D43 D44 D45 X D46 X D47 X D48 D49 D50 D51 D52 X D53 X D54 X D55 X D56 IM D57 X D58 X D59 D60 X 0 D61 1 D62 1 D63 0
AD1 AD2 AD3 AD4 AD5
RA0 RA1 RA2 RA3
X: don't care
RA0 to RA3: ADRAM address
RA0 RA1 RA2 RA3 LSB Least significant bit MSB Most significant bit
AD1 to AD5: ADATA display data In addition to the 5 x 7, 5 x 8, or 5 x 9 dot matrix display data (MDATA), this LSI supports direct display of the five accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM. The figure below shows the correspondence between the data and the display. When ADn = 1 (where n is an integer between 1 and 5) the segment corresponding to that data will be turned on.
ADATA
Corresponding output pin S5m + 1 (m is an integer between 0 and 11) S5m + 2 S5m + 3 S5m + 4 S5m + 5
(m is an integer between 0 and 11)
AD1 AD2 AD3 AD4 AD5
No. 5915-14/27
LC75811E, 75811W IM: Setting the method of writing data to ADRAM
IM 0 1 ADRAM data write method Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.) Increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.)
Notes: *14. * ADRAM data write method when IM = 0
CCB address (4) 24 bits Instruction execution time
CCB address (4) 24 bits Instruction execution time
CCB address (4) 24 bits Instruction execution time ADRAM data write finishes
CCB address (4) 24 bits
Instruction execution time ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
* ADRAM data write method when IM = 1 (Instructions other than the "ADRAM data write" instruction cannot be used.)
CCB address (4) 24 bits Instruction execution time
CCB address (5) 8 bits
CCB address (5) 8 bits Instruction execution time
CCB address (5) 8 bits Instruction execution time
CCB address (5) 8 bits
CCB address (6) 16 bits Instruction execution time ADRAM data write finishes
Instruction execution time
Instruction execution time
ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
ADRAM data write finishes
Instructions other than the "ADRAM data write" instruction cannot be used.
Data format at (4) (24 bits)
Code D40 D41 D42 D43 D44 D45 X D46 X D47 X D48 D49 D50 D51 D52 X D53 X D54 X D55 X D56 IM D57 X D58 X D59 D60 X 0 D61 1 D62 1 D63 0
AD1 AD2 AD3 AD4 AD5
RA0 RA1 RA2 RA3
X: don't care
Data format at (5) (8 bits)
Code D56 D57 D58 D59 D60 D61 X D62 D63 X X X: don't care
AD1 AD2 AD3 AD4 AD5
Data format at (6) (16 bits)
Code D48 D49 D50 D51 D52 D53 X D54 X D55 X D56 0 D57 X D58 X D59 X D60 0 D61 1 D62 1 D63 0
AD1 AD2 AD3 AD4 AD5
X: don't care
No. 5915-15/27
LC75811E, 75811W * CGRAM data write ...
Code D0 CD1 D1 CD2 D2 CD3 D3 CD4 D4 CD5 D5 CD6 D6 CD7 D7 CD8 D8 CD9 D9 CD10 D10 CD11 D11 CD12 D12 CD13 D13 CD14 D14 CD15 D15 CD16
Code D16 CD17 D17 CD18 D18 CD19 D19 CD20 D20 CD21 D21 CD22 D22 CD23 D23 CD24 D24 CD25 D25 CD26 D26 CD27 D27 CD28 D28 CD29 D29 CD30 D30 CD31 D31 CD32
Code D32 CD33 D33 CD34 D34 CD35 D35 CD36 D36 CD37 D37 CD38 D38 CD39 D39 CD40 D40 CD41 D41 CD42 D42 CD43 D43 CD44 D44 CD45 D45 X D46 X D47 X
Code D48 CA0 D49 CA1 D50 CA2 D51 CA3 D52 CA4 D53 CA5 D54 CA6 D55 CA7 D56 X D57 X D58 X D59 X D60 0 D61 1 D62 1 D63 1 X: don't care
CA0 to CA7: CGRAM address
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 LSB Least significant bit MSB Most significant bit
CD1 to CD45: CGRAM data (5 x 7, 5 x 8, or 5 x 9 dot matrix display data) The bit CDn (where n is an integer between 1 and 45) corresponds to the 5 x 7, 5 x 8, or 5 x 9 dot matrix display data. The figure below shows that correspondence. The dots for which the corresponding data CDn is 1 will be turned on.
CD1 CD6 CD11 CD16 CD21 CD26 CD31 CD36 CD41
CD2 CD7 CD12 CD17 CD22 CD27 CD32 CD37 CD42
CD3 CD8 CD13 CD18 CD23 CD28 CD33 CD38 CD43
CD4 CD9 CD14 CD19 CD24 CD29 CD34 CD39 CD44
CD5 CD10 CD15 CD20 CD25 CD30 CD35 CD40 CD45
Note:*15. CD1 to CD35: 5 x 7 dot matrix display data CD1 to CD40: 5 x 8 dot matrix display data CD1 to CD45: 5 x 9 dot matrix display data
No. 5915-16/27
LC75811E, 75811W Notes on the Power On and Power Off Sequences * At power on: Logic block power supply (VDD) on LCD driver block power supply (VLCD) on * At power off: LCD driver block power supply (VLCD) off Logic block power supply (VDD) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time.
Instruction execution
Initial state settings
Display state
Display off
Display on
Display off
Display on/off control instruction execution (Turning the display on)
Display on/off control instruction execution (Turning the display off)
Initial state settings * t1 0 * t2 > 0 * t3 0 (t2 > t3) * tWRES.....1 s min * Set display technique * DCRAM data write * ADRAM data write (If ADRAM is used.) * CGRAM data write (If CGRAM is used.) * Set AC address Figure 3
No. 5915-17/27
LC75811E, 75811W 1/8 Duty, 1/4 Bias Drive Technique
LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off
LCD driver output when only LCD segments corresponding to COM1 are turned on
LCD driver output when only LCD segments corresponding to COM2 are turned on
LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on
No. 5915-18/27
LC75811E, 75811W 1/9 Duty, 1/4 Bias Drive Technique
LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off
LCD driver output when only LCD segments corresponding to COM1 are turned on
LCD driver output when only LCD segments corresponding to COM2 are turned on
LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on
No. 5915-19/27
LC75811E, 75811W 1/10 Duty, 1/4 Bias Drive Technique
LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned off
LCD driver output when only LCD segments corresponding to COM1 are turned on
LCD driver output when only LCD segments corresponding to COM2 are turned on
LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned on
No. 5915-20/27
LC75811E, 75811W Sample Application Circuit 1 1/8 Duty, 1/4 Bias Drive (For use with normal panels)
LCD panel
C 0.047 F
From the microcontroller
A10729
Sample Application Circuit 2 1/8 Duty, 1/4 Bias Drive (For use with large panels)
LCD panel
C 0.047 F 10 k R 1 k
From the microcontroller
A10730
No. 5915-21/27
LC75811E, 75811W Sample Application Circuit 3 1/9 Duty, 1/4 Bias Drive (For use with normal panels)
LCD panel
C 0.047 F
From the microcontroller
Sample Application Circuit 4 1/9 Duty, 1/4 Bias Drive (For use with large panels)
LCD panel
C 0.047 F 10 k R 1 k
From the microcontroller
No. 5915-22/27
LC75811E, 75811W Sample Application Circuit 5 1/10 Duty, 1/4 Bias Drive (For use with normal panels)
LCD panel
C 0.047 F
From the microcontroller
Sample Application Circuit 6 1/10 Duty, 1/4 Bias Drive (For use with large panels)
LCD panel
C 0.047 F 10 k R 1 k
From the microcontroller
No. 5915-23/27
LC75811E, 75811W Sample Correspondence between Instructions and the Display (When the LC75811-8715 is used)
No. LSB Instruction (hexadecimal) MSB Display Initializes the IC. The display is in the off state. Sets to 1/8 duty 1/4 bias display drive technique Operation
D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63
1
Power application (Initialization with the RES pin.) Set display technique 0 DCRAM data write (increment mode) 0 2 0 0 1 A 8
2
3
Writes the display data " " to DCRAM address 00H
4
DCRAM data write (increment mode) 3 DCRAM data write (increment mode) 1 DCRAM data write (increment mode) E DCRAM data write (increment mode) 9 DCRAM data write (increment mode) F DCRAM data write (increment mode) 0 DCRAM data write (increment mode) C DCRAM data write (increment mode) 3 DCRAM data write (increment mode) 9 DCRAM data write (increment mode) 0 DCRAM data write (increment mode) 0 DCRAM data write (increment mode) C DCRAM data write (increment mode) 3 DCRAM data write (increment mode) 7 DCRAM data write (increment mode) 5 DCRAM data write (increment mode) 8 DCRAM data write (increment mode) 1 DCRAM data write (increment mode) 1 3 0 A 3 3 3 3 4 4 2 2 4 5 4 2 4 5 4 4 5
Writes the display data "S" to DCRAM address 01H
5
Writes the display data "A" to DCRAM address 02H
6
Writes the display data "N" to DCRAM address 03H
7
Writes the display data "Y" to DCRAM address 04H
8
Writes the display data "O" to DCRAM address 05H
9
Writes the display data " " to DCRAM address 06H
10
Writes the display data "L" to DCRAM address 07H
11
Writes the display data "S" to DCRAM address 08H
12
Writes the display data "I" to DCRAM address 09H
13
Writes the display data " " to DCRAM address 0AH
14
Writes the display data " " to DCRAM address 0BH
15
Writes the display data "L" to DCRAM address 0CH
16
Writes the display data "C" to DCRAM address 0DH
17
Writes the display data "7" to DCRAM address 0EH
18
Writes the display data "5" to DCRAM address 0FH
19
Writes the display data "8" to DCRAM address 10H
20
Writes the display data "1" to DCRAM address 11H
21
Writes the display data "1" to DCRAM address 12H
Continued on next page.
No. 5915-24/27
LC75811E, 75811W
Continued from preceding page.
No. LSB Instruction (hexadecimal) MSB Display Operation Loads the DCRAM address 00H and the ADRAM 0 2 SANYO LSI address 0H into AC Turns on the LCD for all digits (12 digits) in MDATA L
D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63
22
Set AC address 0 0
23
Display on/off control F F F X 1 4
24
Display shift 1 Display shift 1 Display shift 1 Display shift 1 Display shift 1 Display shift 1 Display shift 1 Display on/off control 0 0 0 X 8 4 C C C C C C C
SANYO
LSI
Shifts the display (MDATA only) to the left
25
ANYO
LSI
LC
Shifts the display (MDATA only) to the left
26
NYO
LSI
LC7
Shifts the display (MDATA only) to the left
27
YO
LSI
LC75
Shifts the display (MDATA only) to the left
28
O
LSI
LC758
Shifts the display (MDATA only) to the left
29
LSI
LC7581
Shifts the display (MDATA only) to the left
30
LSI
LC75811
Shifts the display (MDATA only) to the left
31
Set to power saving mode, turns off the LCD for all digits LSI LC75811
32
Display on/off control F F F X 1 4
Turns on the LCD for all digits (12 digits) in MDATA Loads the DCRAM address 00H and the ADRAM address 0H into AC X: don't care
33
Set AC address 0 0 0 2
SANYO
LSI
Note: *16. This example above assumes the use of 12 digits 5 x 7 dot matrix LCD. CGRAM and ADRAM are not used.
No. 5915-25/27
LC75811-8715 Character Font (Standard)
LC75811E, 75811W
No. 5915-26/27
A10735
LC75811E, 75811W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 1998. Specifications and information herein are subject to change without notice. PS No. 5915-27/27

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